1. Field of Invention
The present invention relates to a method for manufacturing dynamic random access memory (DRAM). More particularly, the present invention relates to the manufacturing of a DRAM capacitor that has a larger electrode surface area for increasing the memory storage capacity of a DRAM.
2. Description of Related Art
As microprocessors become more powerful and the amount of software data that need to be processed becomes very large, the amount of memory necessary for storing data becomes great. FIG. 1 is a circuit diagram showing a DRAM memory unit. A DRAM memory unit comprises a pass transistor 10 and a storage capacitor 11. The source terminal of the pass transistor 10 is connected to a bit line 12, the gate terminal is connected to a word line 13, and the drain terminal is connected to the storage electrode, known also as the lower electrode 14, of a storage capacitor 11. The plate electrode 15, also known as an upper electrode or a cell plate, is connected to a fixed voltage source. Between the storage electrode 14 and the plate electrode is a dielectric thin film 16.
A capacitor is at the "heart" of a DRAM storage device. When the amount of electric charges capable of being stored in the capacitor is large, soft errors produced by .alpha.-particles can be greatly lowered. Furthermore, a large charge storage capacity in the DRAM capacitor is able to lower its refreshing frequency. In general, the method of increasing the charge storage capacity in a capacitor includes: (1) increasing the dielectric constant of the dielectric layer so that the amount of charges stored in unit area of the capacitor is also increased; (2) reducing the thickness of the dielectric layer, however, there is a minimum thickness for any dielectric material, and under which the quality of the dielectric layer formed will be compromised; (3) increasing the electrode surface area of a capacitor so that more electric charges can be stored in the same capacitor, however, this will cause a lowering of the level of integration for DRAMs.
When a small charge storage capacity is needed in a DRAM capacitor, a conventional two-dimensional or a planar type of capacitor can be fabricated in the integrated circuit. However, a planar type capacitor occupies a rather large surface area on the semiconductor substrate surface, hence is not suitable for high level of integration. Therefore, three-dimensional capacitors, for example, the so-called stacked type or trench type capacitors, are used for increasing the level of integration of DRAMs. Nowadays, even the simple three-dimensional capacitor design is insufficient to provide the necessary capacitance. Consequently, methods of producing DRAM capacitors that can increase the surface area of its electrode within a given substrate area are still being developed.
FIGS. 2a through 2d are cross-sectional views showing the progression of manufacturing steps in the fabrication of a trench-type DRAM capacitor according to a conventional method. First, as shown in FIG. 2a, a substrate 200 having a field oxide layer 201, gate 202, exposed source/drain regions 203, 204 and 205, and an insulating layer 206 that covers the gate 202 already formed thereon, is provided. Next, a first polysilicon layer is formed over the substrate 200, and then patterned to form bit line 207 that is coupled to the source/drain region 204 using photolithographic and etching processes. Subsequently, a second insulating layer 208 is deposited over the substrate 200. Then, using a mask, the second insulating layer 208 is patterned and etched into a layer that covers only the bit line 207 while exposing the source/drain region 205.
Next, as shown in FIG. 2b, a thin impurities-doped first polysilicon layer 209 is formed over the substrate and the second insulating layer 208, and connected to the source/drain region 205. Later, a photoresist layer 210 is coated over the first polysilicon layer 209, then patterned with a mask and etched to form a via 211. Thereafter, oxide material is deposited into the via 211 forming an oxide layer 212.
Next, as shown in FIG. 2c, the photoresist layer 210 is removed. Then, a thin impurities-doped second polysilicon layer 213 is formed.
Next, as shown in FIG. 2d, a portion of the second polysilicon layer 213 that locates over the top of the oxide layer 212 is removed exposing the oxide layer 212. Then, the oxide layer 212 between the second polysilicon layer 213 is also removed to form the storage electrode of the capacitor, which is also electrically coupled to the source/drain region 204. Subsequently, a dielectric layer is formed over the surface of the storage electrode, and then an impurities-doped third polysilicon layer is formed over the dielectric layer to form the plate electrode. Finally, after performing the subsequent processing operations such as the formation of a metallic contact and a protective insulating layer, the DRAM capacitor structure is complete.
FIG. 3 is a cross-sectional view of a conventional stacked type DRAM capacitor structure First, a semiconductor substrate 30 having a metallic oxide semiconductor (MOS) transistor 32 already formed thereon is provided. The MOS transistor includes a gate terminal 33, source/drain regions 34 and spacers 35. On top of the substrate 30, there is a field oxide layer 36 and a conductive layer 37. Next, insulating material is deposited over the substrate to form an insulating layer 38, and then the insulating layer 38 is etched to form contact windows at designated locations above the source/drain regions 34. Thereafter, a lower electrode 39, a dielectric layer 310 and an upper electrode 311 are sequentially formed above the contact windows to form a stacked capacitor structure 312. The dielectric layer 310 can be a silicon nitride/silicon dioxide (NO) composite layer or a silicon dioxide/silicon nitride/silicon dioxide (ONO) composite layer. The lower electrode 39 and the upper electrode 311 can be polysilicon layers. Furthermore, the lower electrode 39 can have an undulating and non-planar profile. Finally, subsequent processing operations such as the formation of a metallic contact and protective insulating layer are performed to complete the DRAM capacitor structure.
At present, the conventional method of improving the storage capacity of a DRAM capacitor mainly relies on the manufacture of capacitor having all kinds of rough and uneven electrode surfaces. Although such method is capable of increasing the capacitance of a capacitor a little, it is insufficient to meet the demand for higher capacitance or to provide the capacitance for a miniaturized device. Besides, many complicated and repetitive processing steps are required for their fabrication.
In light of the foregoing, there is a need in the art to provide a better DRAM capacitor structure and method of manufacture.